Freescale Semiconductor /SKEAZN84 /PWT /R1

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Interpret as R1

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)PWTOV 0 (0)PWTRDY 0 (0)PWTSR 0 (0)POVIE 0 (0)PRDYIE 0 (0)PWTIE 0 (0)PWTEN 0 (000)PRE0 (00)EDGE 0 (00)PINSEL 0 (0)PCLKS 0PPW

PWTOV=0, POVIE=0, PWTSR=0, PWTEN=0, PINSEL=00, EDGE=00, PRE=000, PWTIE=0, PRDYIE=0, PWTRDY=0, PCLKS=0

Description

Pulse Width Timer Register 1

Fields

PWTOV

PWT counter overflow

0 (0): PWT counter no overflow.

1 (1): PWT counter run from 0xFFFF to 0x0000.

PWTRDY

PWT pulse width valid

0 (0): PWT pulse width register(s) is not up-to-date.

1 (1): PWT pulse width register(s) has been updated.

PWTSR

PWT Soft Reset

0 (0): No action taken.

1 (1): Writing 1 to this bit will perform soft reset to PWT.

POVIE

PWT counter overflow interrupt enable

0 (0): Disable PWT to generate interrupt when PWTOV is set.

1 (1): Enable PWT to generate interrupt when PWTOV is set.

PRDYIE

PWT pulse width data ready interrupt enable

0 (0): Disable PWT to generate interrupt when PWTRDY is set.

1 (1): Enable PWT to generate interrupt when PWTRDY is set.

PWTIE

PWT module interrupt enable

0 (0): Disables the PWT to generate interrupt.

1 (1): Enables the PWT to generate interrupt.

PWTEN

PWT Module Enable

0 (0): The PWT is disabled.

1 (1): The PWT is enabled.

PRE

PWT Clock Pre-scaler(CLKPRE) Setting

0 (000): Clock divied by 1.

1 (001): Clock divied by 2.

2 (010): Clock divied by 4.

3 (011): Clock divied by 8.

4 (100): Clock divied by 16.

5 (101): Clock divied by 32.

6 (110): Clock divied by 64.

7 (111): Clock divied by 128.

EDGE

PWT input edge sensitivity

0 (00): The first falling edge starts the pulse width measurement, upon all the following falling edges, the pulse width is captured.

1 (01): The first rising edge starts the pulse width measurement, upon all the following rising and falling edges, the pulse width is captured.

2 (10): The first falling edge starts the pulse width measurement, upon all the following rising and falling edges, the pulse width is captured.

3 (11): The first rising edge starts the pulse width measurement, upon all the following rising edges, the pulse width is captured.

PINSEL

PWT Pulse Inputs Selection

0 (00): PWTIN[0].

1 (01): PWTIN[1].

2 (10): PWTIN[2].

3 (11): PWTIN[3].

PCLKS

PWT Clock Source Selection

0 (0): Bus clock is selected as the clock source of PWT counter.

1 (1): Alternative clock is selected as the clock source of PWT counter.

PPW

Positive Pulse Width

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